Our paper, “A resource- and energy-efficient time-bin-synchronized event-driven SNN accelerator on FPGA,” has been accepted for publication in IEEE Embedded Systems Letters (ESL).

Abstract: Dynamic vision sensors (DVSs) generate sparse asynchronous events only when local brightness changes occur, making their output naturally compatible with spiking neural networks (SNNs) for low-latency and energy-efficient edge inference. However, fine-grained hidden-spike generation can introduce considerable control, buffering, and inter-layer datamovement overhead in lightweight event-driven accelerators. This letter presents a time-bin-synchronized event-driven SNN accelerator that accumulates raw events within each time bin and generates hidden spikes only at bin boundaries. A unified two-event neuron update, neuron-group shared weight banks, and an inter-layer time-bin pipeline are employed to improve event throughput and memory efficiency. A 4-bit 1024-256-10 SNN is implemented on an Artix-7 XC7A100T using 14,275 LUTs, 9,325 FFs, and 32 BRAMs. RTL-characterized evaluation over the complete N-MNIST test set shows that timebin synchronization reduces hidden-spike checks by 85.66%, while inter-layer pipelining reduces the T=300 cycle count by 41.4%. At T=150, the accelerator achieves 97.26% accuracy and 25.06 MEvents/s at 100 MHz; T=300 improves accuracy to 97.65% with 21.11 MEvents/s. The implemented datapath achieves 7.46 GSOP/s peak performance with a 0.296-W post-implementation power estimate. Additional 4-bit evaluations achieve 96.28–97.91% accuracy across N-MNIST networks with H=128-512 and 71.88% on the 32 × 32 DVS128-Gesture configuration.