Our paper, “SABLE: Sign-Based Adaptation for Bayesian Low-Rank Estimation on Edge FPGAs,” has been accepted for publication in IEEE Transactions on Circuits and Systems for Artificial Intelligence (TCASAI).

Abstract: Deploying uncertainty-aware edge intelligence in safety-critical internet of things (IoT) applications is fundamentally bottlenecked by the prohibitive hardware costs of Bayesian neural networks (BNNs). Specifically, practical fieldprogrammable gate array (FPGA) deployments suffer from the memory overhead of multi-pass inference, the datapath complexity of continuous Gaussian sampling, and the pipeline disruptions caused by topology-aware integration. While low-rank adaptation (LoRA) reduces parameter overhead, the reliance on complex random number generation persists. This paper presents SABLE (Sign-based Adaptation for Bayesian Low-rank Estimation), a hardware-algorithm co-design framework that eliminates continuous posterior sampling during deployment. Guided by the Central Limit Theorem, SABLE confines Bayesian stochasticity to a low-rank adapter and approximates Gaussian posteriorpredictive projections through hardware-friendly binary sign perturbations. This mechanism is instantiated via a sign-selection projection datapath driven by lightweight Linear Feedback Shift Registers (LFSRs), transforming heavy probabilistic arithmetic into efficient bitwise accumulation. To scale this mechanism, a topology-aware integration strategy utilizing intra-block streaming fusion maps these stochastic components onto heterogeneous lightweight operators without stalling deterministic pipelines. Experiments demonstrate that SABLE successfully enables fullnetwork uncertainty-aware inference on MobileNetV2-class backbones, significantly improving out-of-distribution detection and prediction reliability while preserving deterministic-path accuracy and maintaining real-time uncertainty-aware throughput.