Our paper, “Hardware-Aware Early Termination for Low-Latency Spiking Neural Network Inference,” has been accepted for publication in IEEE Access.

Abstract: Spiking Neural Networks (SNNs) provide a natural computation model for neuromorphic hardware, but fixed-timestep inference can execute substantial redundant temporal computation. This work proposes a hardware-aware early termination (ET) framework that determines the stopping time from accumulated output-spike statistics without exporting internal continuous neuron states to the termination controller. A spike-ratio confidence metric is combined with a minimum observation timestep to suppress low-evidence early decisions. To improve the temporal quality of the output spikes used by ET, Time-Weighted Spike Alignment Training (TW-SAT) applies stronger supervision to earlier instantaneous output spikes through a normalized exponentially decaying schedule. Experiments on MNIST, Fashion-MNIST, N-MNIST, and DVS128 Gesture are repeated with three independently trained models. At comparable accuracy, dynamic ET consistently requires fewer executed timesteps than validation-selected fixed cutoffs. On MNIST, ET with TW-SAT reaches 98.53 ± 0.05% accuracy with an average of 2.04 ± 0.01 timesteps under an algorithm-level Tmax = 100 setting. A complete FPGA implementation on an Artix-7 device preserves timing closure with only 1.68% additional LUTs and 1.86% additional FFs. Under the deployed Tmax = 20 hardware configuration, cycle-accurate simulation shows that ET reduces the average latency from 12.74 μs to 3.35 μs and increases effective throughput from 78.5 to 298.5 kFPS, corresponding to a 3.80× improvement. These results show that output-spike-based termination provides a low-overhead control path for reducing SNN inference latency while retaining a spike-observable hardware interface.