Robust Training to Secure Automated AI Accelerator Generation Against Malicious Platforms

C. Guo and Y. Shi

International Conference on Neural Information Processing (ICONIP), Nov. 2025, pp. 76–89.

Bennet’s Doubler-Extended Converter With Optimized Bias for Enhanced Energy Extraction From Triboelectric Nanogenerators

Y. Su and Y. Shi

IEEE Transactions on Power Electronics (IF: 7.1), vol. 40, no. 9, pp. 12026 – 12030, 2025.

DSE-Based Hardware Trojan Attack for Neural Network Accelerators on FPGAs

C. Guo, M. Yanagisawa, and Y. Shi

IEEE Transactions on Neural Networks and Learning Systems (IF: 9.7), vol. 26, no. 7, pp. 13036 – 13050, 2025.

A Novel Security Threat Model for Automated AI Accelerator Generation Platforms

C. Guo and Y. Shi

IEEE Access (IF: 4.2), vol. 13, pp. 61237 – 61249, 2025.

An FPGA-Based YOLOv6 Accelerator for High-Throughput and
Energy-Efficient Object Detection

X. Sha, M. Yanagisawa, and Y. Shi

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, vol. e-108A, no. 3, pp. 473- 481, 2025.

An Efficient Multiplier-Less Processing Element on Power-of-2 Dictionary-Based Data Quantization

J. Li, M. Yanagisawa, and Y. Shi

Integrated Circuits and Systems, vol. 1, no. 1, pp. 53- 62, 2024.

A Dual-Output Rectifier-Based Self-Powered Interface Circuit for Triboelectric Nanogenerators

Y. Su, M. Yanagisawa, and Y. Shi

IEEE Transactions on Power Electronics (IF: 6.6), vol. 39, no. 6, pp. 6630 – 6634, 2024.

Dataflow Optimization through Exploring Single-Layer and Inter-Layer Data Reuse in Memory-Constrained Accelerators

J. Ye, M. Yanagisawa, and Y. Shi

Electronics, vol. 11, no. 15, 2022.

Power-Efficient Deep Convolutional Neural Network Design Through Zero-Gating PEs and Partial-Sum Reuse Centric Dataflow

L. Ye, J. Ye, M. Yanagisawa, and Y. Shi

IEEE Access (IF: 3.476), vol. 9, pp. 17411 – 17420, 2021.

Transition Detector-Based Radiation-Hardened Latch for Both Single- and Multiple-Node Upsets

S. Tajima, M. Yanagisawa, and Y. Shi

IEEE Transactions on Circuits and Systems II: Express Briefs (IF: 3.691), vol. 67, no. 6, pp. 1114 – 1118, 2020.

Robust Secure Scan Design Against Scan-Based Differential Cryptanalysis

Y. Shi, N. Togawa, M. Yanagisawa, and T. Ohtsuki

IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 20, no. 1, pp. 176 – 181, 2012.

Improved Launch for Higher TDF Coverage With Fewer Test Patterns

Y. Shi, N. Togawa, M. Yanagisawa, and T. Ohtsuki

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 29, no. 8, pp. 1294 – 1299, 2010.